Switches are known that receive data on one or more input ports and supply the data at one or more output ports. Such switches may include an input stage, which receives the data; an intermediate stage, which includes a switch fabric; and an output stage that supply the data to the output ports. Typically, the data is grouped in data units and the switch fabric simultaneously switches a plurality of such data units at a given time. Each data unit may be associated with a particular time slot.
However, the data units may arrive at different input ports at different times, such that various data units may be delayed or skewed relative to one another. In addition, the lengths of paths extending from various input ports to corresponding output ports of the switch may also differ. As a result, data units propagating through the switch may be skewed relative to one another for this reason also. Accordingly, data units may be supplied to the switch fabric at different times, such that simultaneous switching of such data unit groups by the switch fabric may be difficult to achieve.
In one technique that may be used to insure simultaneous switching by the switch fabric, each data unit may be provided to a corresponding first-in-first-out (FIFO) buffer prior to being supplied to the switch fabric. Each FIFO is then “filled” whereby symbols or data units are sequentially fed to the FIFO and stored in corresponding stages or portions thereof. Since the data units may be supplied to the FIFO at different times, certain FIFOs may begin to “fill” or be “pre-filled” with data before others. When one of the FIFOs receives the “slowest” data unit, i.e., that data unit group with the greatest delay or skew relative to the other data units, each of the remaining FIFOs sequentially outputs the pre-filled data stored therein. Thus, each FIFO simultaneously outputs the data of each data unit, and each data unit group is therefore temporally aligned prior to being input to the switch fabric. The switch fabric can then simultaneously switch the incoming data unit groups.
In certain instances one or more of the data units supplied to the FIFO buffers may be unavailable or “missing”, for example, because the corresponding input port is disconnected or a data unit group circuit provided in the switch cannot identify a boundary or edge of an input data unit group supplying data units to the switch. In that case, the FIFOs that receive data, will, as noted above, output data to the switch fabric once the slowest data unit is received by a corresponding FIFO.
If the slowest data unit is the missing data unit group, however, the remaining FIFOs may not pre-fill a sufficient amount of data before being supplied to the switch fabric. Accordingly, when the slowest data unit group is supplied to its corresponding FIFO, i.e., the slowest data unit becomes “available”, the other data units may be output to the switch fabric before the slowest data unit is supplied to its corresponding FIFO. The slowest data unit, therefore, will lag the remaining data units, such that not all data units input to the switch fabric will be temporally aligned, and the switch fabric may not be able to simultaneously switch each of the incoming data units.
An apparatus and related method is therefore needed wherein data units are temporally aligned prior to input to the switch fabric, regardless of whether the slowest data unit is available.